Design and analysis of matching circuit architectures for a closest match lookup

verfasst von

Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias Noll, John McCanny

Abstract

This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.

Externe Organisation(en)

Rheinisch-Westfälische Technische Hochschule Aachen (RWTH)
Queen's University Belfast

Typ

Aufsatz in Konferenzband

Publikationsdatum

26.06.2006

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Ingenieurwesen (insg.)

Elektronische Version(en)

https://doi.org/10.1109/IPDPS.2006.1639481 (Zugang: Geschlossen)
http://www.cecs.uci.edu/~papers/ipdps06/pdfs/71-RAW-paper-1.pdf (Zugang: Offen)